04/26/21 - KDT

LFSD_768_SIOD_042621.mcs contains:

Master_768_SIOD_wBoot_0042621.bit (Master_768_SIOD_v3_r0_042621.bit) FPGA ID 0x0B370300

Slave_768_SIOD_v2_r1_011121.bit FPGA ID 0x00B70201

In this design I modified MB_Master_OpAmpEn_proc to synchronize PCIe_PCIe_Master_OpAmp_En to AXI_clk
so that we can capture Master_OpAmp_En going low in both the PCIe and Microblaze clock domains.

Additionally, I changed the I2C Temperature comparisons to occur in te Microblaze clock domain (100MHz)
versus the LFSD Clocks Domain (250MHz) as we were witnessing bits not switching
synchronously - causing a 1 LFSD_clk misread which triggered a Over Temp Error
which results in power-down the OpAmp board.

I also modified the Microblaze App to add 2 menu items to Simulate the Temperature redeadings
crossing Byte Boundaries - specifically 0x0FE <--> 0102.

Master_768_SIOD_App_042421.mcs